What is 1.6T Ethernet? A Q&A for network and test engineers

The industry's next bandwidth milestone has a name:1.6T Ethernet. As the technology moves from standards development and lab validation toward early commercial deployment, network architects, lab managers and design teams need to understand what changes are coming along with 1.6T. They also need to understand what those changes mean for AI data center infrastructure. In part one of this two part Q&A series on 1.6T Ethernet, I introduce 1.6TE and answer the questions we hear most from teams evaluating the technology.

What is 1.6T Ethernet?

1.6T Ethernet (i.e., 1.6 Terabit Ethernet) is the next rung on the ever-accelerating Ethernet bandwidth ladder. It is being defined through the IEEE P802.3dj amendment, the IEEE 802.3 working group developing the next amendment to the Ethernet standard for 200G, 400G, 800G and 1.6T Ethernet. And yes, you read that correctly: “dj” is part of the part of the project designation name—a fitting name for the work setting the beat for the next generation of Ethernet.

The OSFP form factor is well suited to support 1.6T Ethernet, thanks to its inherent support for eight high-speed electrical lanes. The OSFP Multi-Source Agreement has already defined the OSFP1600 module, which supports eight lanes of 200Gbit/s. By establishing common mechanical, electrical and thermal specifications, the agreement provides a standardized foundation for developing 1.6T modules across the industry.

To achieve an aggregate data rate of 1.6 Tbit/s, a 1.6T Ethernet interface uses eight 200 Gbit/s lanes in each direction—twice the per-lane data rate used for 800G Ethernet. Put another way, a 1.6T link carries traffic simultaneously across eight separate 200 Gbit/s lanes in each direction.

On the electrical side, new generation SerDes technology, supported by the OIF’s CEI-224G group of specifications, enables signaling rates of approximately 224 Gbit/s per lane using PAM4 modulation. This higher signaling rate of 224 Gbit/s accommodates the protocol and FEC overhead needed to support an Ethernet lane rate of 200 Gbit/s.

1.6T pluggables are emerging in several optical configurations, including DR8, 2 x DR4, and 2 x FR4. Each carries eight 200 Gbit/s lanes, with configurations designed to support different fiber architectures and reaches—from parallel singlemode fiber links spanning hundreds of meters to wavelength-division multiplexed links reaching up to 2 km. These modules are being developed to align with the emerging IEEE 802.3dj specifications and use a CMIS-compliant management interface over I2C. This provides a common framework for configuration, diagnostics, monitoring, and firmware management, helping 1.6T modules work with the same management tooling already known from previous technologies such as 400G and 800G.

How is 1.6T Ethernet different from previous Ethernet rates?

The key difference between 1.6T Ethernet and 800G Ethernet is the move to eight 200 Gbit/s PAM4 lanes. While Ethernet capacity has traditionally increased by either adding lanes, increasing the data rate per lane, or both, 1.6T Ethernet retains the eight-lane architecture used by 800G and doubles the per-lane data rate from 100 Gbit/s to 200 Gbit/s.

At that higher symbol rate, there are significantly greater implementation challenges such as signals encountering greater insertion loss, noise sensitivity, and intersymbol interference (ISI). This requires more advanced transmitter and receiver equalization to maintain reliable signal performance.

To support longer-reach applications, forward error correction (FEC) must evolve alongside the physical interface. Previous 100 Gbit/s-per-lane Ethernet implementations typically rely on the outer Reed-Solomon FEC used by the Ethernet physical coding sublayer. For many 200 Gbit/s-per-lane PHYs, IEEE P802.3dj introduces a concatenated FEC architecture in which an inner FEC layer corrects errors closer to the physical lane before passing the data to the outer FEC layer. This additional inner FEC layer is a key change from conventional 400G and 800G implementations. As a result, a complete 1.6T Ethernet test plan may need to evaluate inner-FEC performance, outer-FEC performance, and the interaction between the two—not simply the final post-FEC bit error rate.

There are a couple of other important differentiators. One important differentiator is symbol multiplexing, where FEC symbols rather than individual bits are distributed across the physical lanes.

Another key difference is that link training, although still optional in some cases, is more important and sometimes mandatory for certain interfaces (i.e. electrical interfaces). However, the definition and terminology of this parameter negotiation are evolving toward a more detailed and comprehensive exchange, potentially involving one or more inter-sublayer links (ISLs), and the process is also being renamed to autonomous path startup (APSU).

Why is 1.6T Ethernet important for data center interconnect networks?

AI infrastructure is a major driver of the transition to 1.6T Ethernet. Larger GPU clusters and increasingly distributed AI workloads require more bandwidth for scale-out connections within data centers and scale-across connections between data centers. By increasing each Ethernet port from 800 Gbit/s to 1.6 Tbit/s, next-generation switches and optical modules can move twice as much data per port while supporting the higher network density required by AI fabrics.

Copper has run out of road—or at least much of it. As per-lane rates climb, practical electrical reach shrinks. Transmitting a 224G-class signal over copper beyond very short distances is already a significant engineering challenge, which is why the industry keeps moving optics closer to the switch ASIC.

Power is the other constraint engineers can't ignore. DSP-based 1.6T pluggables carry a real energy cost, and power is becoming a first-order design input rather than a footnote. The pressure to reduce energy per bit is opening the door to linear pluggable optics (LPO) and linear receive optics (LRO), which remove the conventional module DSP to reduce power, latency and heat. The exact power savings (could be up to 50%) depend on implementation, but this tradeoff is already shaping next-generation 1.6T module architecture and design decisions.

For data center interconnects (DCI) specifically, 1.6T matters because it allows operators to double effective port bandwidth without doubling the number of physical ports, transceivers, or rack-unit footprint. Depending on the optical configuration, it may also reduce the number of fiber connections required for a given aggregate capacity—a meaningful advantage as facility power and space budgets tighten even as AI traffic continues to grow.

1.6T Ethernet brings the bandwidth density AI infrastructure needs, but it also raises the bar for signal integrity, FEC performance, thermal management, and interoperability. In part two, we’ll look at what these challenges mean for 1.6T Ethernet testing—and the capabilities engineers need to validate performance with confidence.